With the high development of computer technology and integrated circuit technology, high performance computer system has increasingly become a development need of an economic society. This brings huge challenge to the design difficulty of the computer system, such as for example, data transmission rate of the system interconnection and data transmission bandwidth all reach an unprecedentedly level. Where the system interconnection includes chips, boards and systems. Currently, transmission frequency among key chip groups of the computer system reaches nearly 10 GHz, data transmission bandwidth reaches dozens GB/s, high speed signal transmission rate reaches about 10 Gbps, and high speed signal transmission bandwidth also reaches dozens channels. The high speed signal adopts differential signal to transmit, which exacerbates a huge amount of signal lines and brings huge challenge to chip design, PCB design and system design. For example, the bandwidth of QPI interface serial data signal reaches 20 channels, and each channel adopts differential signal to transmit. Therefore, this brings huge problem to differential high speed transmission design of serial data multi-channel among chips. On the one hand, high bits wide serial data differential signal brings challenge to PCB design of the system, and due to the signal quality requirement, multi-channel signal cannot be strictly sorted and wired. On the other hand, in multiprocessor system, one motherboard can be integrated with multiple processors or other chip groups, resulting in that multi-channel high speed port cannot be sorted and wired, some of the ports have to be staggered, and even the differential signal reverse to be wired. The aforementioned challenges bring great complexity for PCB design and chips design and verification, and seriously affect the design and verification period of the system. Therefore, design a differential signal reversion and correction circuit inside the chip can effectively solve the problem.